The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to an interconnect level that includes a crack stop region that laterally surrounds an active device and a wiring region, wherein the crack stop region contains a dielectric material that has a higher dielectric constant than the interconnect dielectric material of the wiring region.
Integrated circuits are generally created by forming an array of electronic devices (i.e., transistors, diodes, resistors, capacitors, etc.) and interconnect wiring structures on a semiconductor substrate. Generally, semiconductor devices and gates are formed in a first layer during front-end-of-line (FEOL) processing, followed by formation of interconnect wiring structures in a second layer by BEOL processes. These first and second layers can each contain multiple layers of dielectric material which electrically isolate the devices and interconnect structures. Advanced BEOL processes utilize interconnect dielectric materials with a low dielectric constant (low-k) to minimize interconnect parasitic capacitances. The term “low-k” is used herein to denote a dielectric material having a dielectric constant of less than 4.0 (i.e., the dielectric constant of silicon dioxide).
After a plurality of integrated circuits (ICs) are formed on a semiconductor wafer, the semiconductor wafer is subjected to a wafer cutting process so as to divide the semiconductor wafer into a plurality of semiconductor chips. The semiconductor chips are then bonded to a substrate package. Due to poor mechanical strength and poor moisture insulation of the low-k interconnect dielectric materials during the wafer cutting and bonding processes, cracks can form and propagate through the interconnect dielectrics toward the active area of the IC chip, causing chip failure.
In order to avoid such crack formation, propagation and structural failure, crack stop regions have been specifically designed which laterally surround each active device and interconnect region. New challenges arise on the crack stop for leading edge technologies. For example, as technologies scale down to 14 nm, 10 nm, 7 nm and beyond, the via sizes at the lower levels become very small (less than, or equal to, 32 nm). The via to line contact area becomes so small that the crack stop toughness may not meet the requirement anymore and result in a crack stop breach. To solve this problem, much larger via (so-called via bars) sizes in the crack stop region are needed. This may cause process window concerns for very different via sizes at different areas of the same interconnect level. There thus exists a need to provide an advanced interconnect structure that has improved crack stop capability.